图书简介
The second edition of VLSI Design is a comprehensive textbook designed for undergraduate students of electrical, electronics, and electronics and communication engineering. It provides a thorough understanding of the fundamental concepts and design of VLSI systems.
Preface; Preface to the First Edition; List of Colour Plates; 1 Introduction to VLSI Systems; 1.1 Historical Perspective; 1.2 Introduction to IC Technology; 1.3 Types of Integrated Circuits; 1.4 Design Methodology; 1.5 Design DomainsY-Chart; 1.6 Hierarchical Abstraction; 1.7 Design Flow; 1.8 Design Styles; 1.9 Computer-aided Design; 1.10 CMOS Integrated Circuit; 1.11 Issues with Integrated Circuits at the DSM Level; 1.12 Modelling and Simulation; 1.13 Design Metrics; 1.14 Cost of Integrated Circuits; 1.15 CAD Tools for VLSI Design; 1.16 VLSI Design using Computer-aided Design Tools; 1.17 Problems in VLSI CAD Domain; 1.18 IC Chip IndustryA Brief Outlook; 1.19 Recent Developments and Future Projections; 2 MOS Transistors; 2.1 Introduction to Semiconductor Devices; 2.2 Charge Carriers in Semiconductors; 2.3 Parallel Plate Capacitor; 2.4 MOS Capacitor; 2.5 MOS Transistor; 2.6 MOSFET Threshold Voltage; 2.7 MOSFET Current Equation; 2.8 MOSFET V-I Characteristics; 2.9 MOSFET Scaling; 2.10 Small Geometry Effects; 2.11 MOSFET Capacitances; 2.12 MOSFET Modelling; 3 MOS Inverters; 3.1 Introduction; 3.2 Voltage Transfer Characteristics; 3.3 Resistive Load Inverter; 3.4 Enhancement-type nMOS Load Inverter; 3.5 Depletion-type nMOS Load Inverter; 3.6 CMOS Inverter; 3.7 Design of Symmetric Inverter; 3.8 Transient Analysis of CMOS Inverter; 3.9 Power Supply Voltage Scaling in CMOS Inverter; 4 Standard Cell Library Design and Characterization; 4.1 Introduction; 4.2 Standard Cell Library; 4.3 Schematic Design; 4.4 Layout Design; 4.5 Layout versus Schematic; 4.6 Extraction from Layout; 4.7 Antenna Effect; 4.8 Standard Cell Library Data; 4.9 Library Characterization; 4.10 Cell Characterization; 4.11 Circuit Simulation; 4.12 Measuring the Propagation Delay; 4.13 Measuring Rise and Fall Time; 4.14 Ring Oscillator; 4.15 Load/Slew Characterization Table; 4.16 Power Characterization; 4.17 Reliability and Noise Characterization; 4.18 Interconnect Delay Modelling; 5 Analog CMOS Design; 5.1 Introduction; 5.2 MOSFET Small Signal Model; 5.3 MOSFET as a Switch; 5.4 MOS Diode/Resistor; 5.5 Small Signal Analysis of Single Stage Amplifiers; 5.6 MOS Current Source and Sink; 5.7 Current Mirror; 5.8 Resistor Realization Using Switched Capacitor; 5.9 MOS Voltage and Current References; 5.10 CMOS Amplifier; 5.11 MOS Differential Amplifier; 5.12 Cascode Amplifier; 5.13 Current Amplifier; 5.14 Output Amplifier; 5.15 Source Follower; 5.16 Voltage Level Shifter; 5.17 CMOS Operational Amplifier; 5.18 Comparator; 5.19 Switched Capacitor Filter; 5.20 Digital-to-Analog Converter; 5.21 Analog-to-Digital Converter; 5.22 Phase-locked Loop; 5.23 Field Programmable Analog Array; 6 Digital CMOS Logic Design; 6.1 Introduction; 6.2 Digital Logic Design; 6.3 CMOS Logic Design; 6.4 CMOS Design Methodology; 6.5 Design of CMOS Inverter (NOT) Gate; 6.6 Design of Two-Input NAND Gate; 6.7 Design of Two-Input NOR Gate; 6.8 Classification of CMOS Digital Logic Circuit; 6.9 Combinational Logic Circuit; 6.10 Sequential Logic Circuit; 6.11 Pseudo-nMOS Logic; 6.12 CMOS Transmission Gate; 6.13 Dynamic CMOS Logic; 6.14 Domino CMOS Logic; 6.15 NORA CMOS Logic; 6.16 Zipper CMOS Logic; 6.17 True Single-phase Clock (TSPC) Dynamic CMOS Logic; 6.18 Pass Transistor Logic; 6.19 Complementary Pass Transistor Logic; 6.20 Voltage Bootstrapping; 6.21 Differential CMOS Logic; 6.22 Adiabatic Logic; 6.23 Dual-threshold CMOS Logic; 7 Semiconductor Memories; 7.1 Introduction; 7.2 Static RAM; 7.3 Dynamic RAM; 7.4 Read Only Memory; 7.5 Flash Memory; 7.6 Content Addressable Memory; 7.7 Design of CAM Architecture; 8 BiCMOS Technology and Circuits; 8.1 Introduction; 8.2 Comparison Between CMOS and BJTs; 8.3 BiCMOS Technology; 8.4 Bipolar Logic; 8.5 BiCMOS Logic Circuits; 8.6 BiCMOS Two-Inputs NAND Logic; 8.7 BiCMOS Two-inputs NOR Logic; 8.8 Complex Logic Using BiCMOS; 8.9 Applications of BiCMOS Circuits; 8.10 Disadvantages of BiCMOS; 8.11 SiliconGermanium BiCMOS Technology; 9 Logic Synthesis; 9.1 Introduction; 9.2 Introduction to Synthesis; 9.3 Transistor-level or Circuit-level Synthesis; 9.4 Logic-level Synthesis; 9.5 Block-level Synthesis or Datapath Synthesis; 9.6 Logic Synthesis; 9.7 Algorithms; 9.8 Boolean Space; 9.9 Binary Decision Diagram (BDD); 9.10 Logic SynthesisAdvantages and Disadvantages; 9.11 How Does It Work?; 9.12 Sequential Logic Optimization; 9.13 Building Blocks for Logic Design; 10 Timing Analysis; 10.1 Introduction; 10.2 Delay in Any System; 10.3 Delay in VLSI Circuits; 10.4 Delay in CMOS Inverter; 10.5 Slew Balancing; 10.6 Transistor Equivalency; 10.7 Case Study: Effect of Transistor Size on Propagation Delay; 10.8 Design of Two-Inputs NAND Gate for Equal Rise and Fall Slew; 10.9 Design of Two-Inputs NOR Gate for Equal Rise and Fall Slew; 10.10 MOS Capacitances; 10.11 Dependency of Delay and Slew on Power Supply Voltage; 10.12 Design Techniques for Delay Reduction; 10.13 Intrinsic Delay of Inverter; 10.14 Inverter Sizing Effect on Propagation Delay; 10.15 Inverter Chain Design; 10.16 Effect of Input Slew on Propagation Delay; 10.17 Delay Dependence on Input Patterns; 10.18 Logical Effort; 10.19 Classification of Digital Systems; 10.20 Definitions of Timing Terms; 10.21 Timing Analysis; 10.22 Timing Models; 10.23 Timing Analysis Goals; 10.24 Timing Analysis at the Chip Level; 10.25 Static vs Dynamic Timing Verification; 10.26 Factors Impacting Timing Delay; 10.27 Static Timing AnalysisCase Study; 10.28 Fixed Delay Model; 10.29 Checking Timing Constraints; 10.30 Timing Verification in Sequential Synchronous Circuits; 10.31 Hierarchical Timing Specification and Verification; 10.32 Issues with Static Delay Modelling; 10.33 First-order Gate Delay Model; 10.34 Parasitic Extraction; 10.35 Timing Convergence Problem; 10.36 Timing-Driven Logic Synthesis; 10.37 Gate and Device Sizing; 10.38 Typical Delay-area Trade-off; 10.39 Timing-driven Layout Synthesis; 11 Physical DesignFloorplanning, Placement, and Routing; 11.1 Introduction; 11.2 Partitioning; 11.3 Floorplanning; 11.4 Placement; 11.5 Routing; 11.6 Types Of Routing; 11.7 Special Routing; 11.8 Multilevel Routing; 11.9 Physical Design EDA Tools; 11.10 Layout Database; 12 Verification and Reliability Analysis; 12.1 Introduction; 12.2 Verification Methodologies in VLSI Design Flow; 12.3 Logic Verification; 12.4 Physical Verification; 12.5 Design Rule Check; 12.6 Layout Versus Schematic (LVS) Check; 12.7 Electrical Rule Check; 12.8 Antenna Check; 12.9 Metal Density Check; 12.10 Layout Extraction; 12.11 Crosstalk Analysis; 12.12 Introduction to Reliability; 12.13 IC ReliabilityDefinitions; 12.14 Reliability Issues in ICs; 12.15 Electromigration; 12.16 Time-dependent Dielectric Breakdown; 12.17 Channel Hot Electron; 12.18 Negative-bias Temperature Instability; 12.19 IR Drop; 12.20 Latch-up; 12.21 Electrical Overstress and Electrostatic Discharge; 12.22 Soft Error; 13 IC Packaging; 13.1 Introduction; 13.2 Types of IC Packages; 13.3 Package Modelling; 13.4 Electrical Package Modelling; 13.5 IC Package Thermal Modelling; 13.6 IC Package Stress Modelling; 13.7 Package Models; 13.8 Package Simulation; 13.9 Flip-chip Package; 14 VLSI Testing; 14.1 Introduction; 14.2 Importance of Testing; 14.3 Fault Models; 14.4 Fault Simulation; 14.5 Design for Testability; 14.6 Ad Hoc Testing; 14.7 Scan Test; 14.8 Boundary Scan Test; 14.9 Built-in Self Test; 14.10 Automatic Test-pattern Generation; 14.11 IDDQ Test; 14.12 Design for Manufacturability (DMF); 14.13 Design Economics; 14.14 Yield; 14.15 Probe Test; 15 Field Programmable Gate Array; 15.1 Introduction; 15.2 Programmable Logic Devices; 15.3 Sequential PLD; 15.4 Complex PLD; 15.5 Field Programmable Gate Array; 15.6 Xilinx SRAM-based FPGA; 15.7 Comparison between FPGA, ASIC, and CPLD; 15.8 FPGA-based System Design; 15.9 IRSIM; 15.10 Generalized Open Source Programmable Logic; 16 VLSI Process Technology; 16.1 Introduction; 16.2 Crystal Growth; 16.3 Photolithography; 16.4 CMOS Technology: n-well and p-well Process; 16.5 Oxidation; 16.6 Diffusion; 16.7 Ion Implantation; 16.8 Etching; 16.9 Epitaxial Growth; 16.10 Metallization; 16.11 Packaging; 17 Subsystem Design; 17.1 Introduction; 17.2 Adders; 17.3 Multipliers; 17.4 Drivers and Buffers; 18 Low Power Logic Circuits; 18.1 Introduction; 18.2 Power Dissipation in Logic Circuits; 18.3 Power Reduction Techniques; 18.4 Low Power Design Techniques; Appendix A Digital Design Using VHDL; Appendix B Digital Design Using Verilog; Appendix C SPICE Tutorial; Appendix D Answers to Objective-type Questions
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